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Mammal: In Logisim

New instructions for Mammal

New Instructions and Their FormatsNN

Note that there is no instruction corresponding to an interrupt.

Finite State Machine for Mammal

The proposed FSM for Mammal is shown below. We have extended bird’s FSM by 7 new states (INT1, INT2, INT3, STI, CLI, RET1, RET2, RET3) to add interrupt processing + 3 new instructions. We have to investigate these new states one by one, and see if the hardware resources provided by mammal is sufficient to implement them. If not, we have to add new hardware to Bird for their implementation. As usual, we will first discuss the hardware without the control unit. We will discuss the control unit last.

Interrupt processing in Mammal

When the reptile receives an interrupt, it has to wait for the termination of the current instruction. Then it doesnt proceed to execute the next instruction, but proceeds to execute the states INT1-INT2-INT3 in a sequence. As discussed before, these three states pushes the PC and zero flag to the stack, disable interrupts, read the interrupt vector,

INT1: This state pushes the program counter to stack (M[SP]<=PC, and SP–) and disable interrupts. Pushing the SP to stack can be readily done in the Bird hardware by activating the control signals, DATAMUX=1, MEMLD=1, ARMUX=2 and SP–=1. But we don’t know yet how to enable/disable interrupts. This will be discussed when we design the control unit. For now, it suffices to know that we will add a new control signal IFRESET, and activate it when we want to disable interrupts. Hence implementing this state requires no changes in the Bird architecture, but it needs the addition of a control signal (IFRESET) to the bird control unit.

INT2: This state pushes the flags to the stack and reads the interrupt vector. Both of these tasks require some additions to the internal structures of bird.

As discussed in the previous chapter, we have to push the zero flag to stack when we receive an interrupt. Conversely, we have to pop it out when we return from an interrupt (in other words, when we execute a RTI instruction). Hence our first order of business is to make the zero flag “pushable” and “popable”.

Pushing the zero flag means writing it to a memory location pointed by the SP, and then decrementing the SP. In order to write the zero flag to memory, the 1-bit witde zero flag must be extended to 16 bits. This is done by constructing a new 16-bit output of ZF register where ZF bit becomes the least significant bit, prefixed with 15 zero bits, ie, by generating the {15’b0,ZF} signal.  When an interrupt comes, this signal is pushed to stack.

Popping the zero flag

  • In order to write the zero flag to memory, we have to extend the zero flag bit to 16-bits by adding 15 0’s to its left.
  • Beforehand, we only write the ZF output of ALU into the ZF flip-flop and this was controlled by the ZFLD control signal. Now, in addition to this, we will also update the same flip-flop with data D[0] coming out from stack during IRET instruction, and this will be controlled by the new control signal, ZFPOP. The new design is sketched below.

Note that, when ZFPOP is active D[0] is written into the flip-flop. When ZFLD is active, ZF is written into the flip-flop. When none of these control signals is active the flip-flop remembers its previous state. When we design the control unit, we should take care that, ZFPOP and ZFLD should not be active simultaneously.

Below, the updated ZF Unit is integrated into the Bird CPUs schematics.

Note that, one of the multiplexer is widened. (açıklanacak)

INT1:

M[SP]<=PC and SP– can be readily done in the Bird hardware by activating the control signals, DATAMUX=1, MEMLD=1, ARMUX=2 and SP–=1. But we don’t know yet how to enable/disable interrupts. This will be discussed when we design the control unit. For now, it suffices to know that we will add a new control signal IFRESET, and activate it when we want to disable interrupts.

INT2:

ARMUX=2, DATAMUX=2, SP–=1, INTLD=1, MEMLD=1, INTACK=1.

INT3:

ARMUX=3, PCMUX=1, PCLD=1.

IRET1:

SP++=1.

IRET2:

ZFPOP=1, ARMUX=2, SP++=1;

IRET3:

ARMUX=2, PCMUX=1, PCLD=1.

STI:

IFSET=1.

CLI:

IFRESET=1.

Control Signals

 

Mammal with Control Unit

 

 

Control Unit

Microcode

The legend “17 control signals” at the top of the figure must be changed to “20-bit control signals”.

Hardware Design

Note that there are 18 control signals. ARMUX and DATAMUX are two bits each, and the rest are one bit each. So our control signals make a total of 20 bits.