VGA Signals

module vga( clk, hsync, vsync, video_on, pixel_tick, pixel_x, pixel_y, reset );
    input wire clk, reset;
    output wire [9:0] pixel_x, pixel_y;
    output wire hsync, vsync, video_on;
    output reg pixel_tick;


     localparam   HD=640, //horizontal display area
                  HF=48,  //horizontal front porch
                  HB=16,  //horizontal back porch
                  HFB=96,  //horizontal flyback
                  VD=480, //vertical display area
                  VT=10,  //vertical top porch
                  VB=33,  //vertical bottom porch
                  VFB=2;  //vertical flyback  


    always @(posedge clk)
        pixel_tick <= ~pixel_tick  //25 MHZ signal is generated.

    assign line_end = h_count == HD+HF+HB+HFB-1;
    assign page_end = v_count == VD+VF+VB+VFB-1;


    always @(posedge pixel_tick)
        if (line end)
            h_count <= 0;
        else
            h_count <= h_count+1;

    always @(posedge(line_end)
        if (page_end)
            v_count <= 0;
        else
            v_count <= v_count+1;

module vga( clk, hsync, vsync, video_on, pixel_tick, pixel_x, pixel_y, reset );

input wire clk, reset;

output wire [9:0] pixel_x, pixel_y;

output wire hsync, vsync, video_on;

output reg pixel_tick;

localparam HD=640, //horizontal display area

HF=48, //horizontal front porch

HB=16, //horizontal back porch

HFB=96, //horizontal flyback

VD=480, //vertical display area

VT=10, //vertical top porch

VB=33, //vertical bottom porch

VFB=2; //vertical flyback

always @(posedge clk)

pixel_tick <= ~pixel_tick //25 MHZ signal is generated.

assign line_end = h_count == HD+HF+HB+HFB-1;

assign page_end = v_count == VD+VF+VB+VFB-1;

always @(posedge pixel_tick)

if (line end)

h_count <= 0;

else

h_count <= h_count+1;

always @(posedge(line_end)

if (page_end)

v_count <= 0;

else

v_count <= v_count+1;

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