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Synchronized I/O 2: Interrupts

Published February 22, 2022

Introduction to Interrupts

Interrupts are an alternative to polling.

Why do we require interrupts?

Basic setup of interrupts

Basic steps of Interrupt processing

The following itemized list shows how an interrupt proceeds step by step. Things that happen in the I/O device is shown in red, if it happened in PIC it is blue, if happened in CPU hardware it is dark green, if happened in sortware it is black.  We will take the keyboard as an example device.

  1. Let somebody press a key of the keyboard. The keyboard will put the character code of the pressed key into its data register and raises its INT pin.

  2. INT pins of all I/O devices are connected to the interrupt request (IRQ) pins of the Programmable Interrupt controller (PIC). If one or more of the PIC’s (unmasked) IRQ pins are raised, INT pin of the PIC is raised, which is connected to the INT pin of CPU. Hence the interrupt signal reaches the CPU.
    The IRQ pins pf the PIC can be individually masked or unmasked by software (that’s why the PIC is called “programmable”). If a particular IRQ pin is masked, the interrupt signal waits there until that particular IRQ pin is unmasked.

  3. IRQ pins of the PIC are numbered from 0 to 7, and this number becomes the “interrupt vector” of the I/O device which is connected to that pin. For example, if the printer is connected to the 5th IRQ pin of PIC, the interrupt vector of the printer becomes 5.

  4. CPU receives the INT signal from the PIC. If its interrupt flag is set, CPU will wait untill an instruction boundary, and then, rather than starting a new instruction, it starts interrupt processing.

  5. CPU disables all interrupts by making IF=0.

  6. CPU raises its INTACK pin to signal that it will read the interrupt vector from PIC. PIC sends the interrupt vector through CPU’s datain bus.

  7. Now CPU has the vector and knows which device had interrupted. It saves the context by pushing PC and FLAGS registers to stack. Then it uses the interrupt vector as an index to IDT to discover the address of the interrupt service routine (ISR, equivalently known as interrupt handler) of the interrupting device, and jumps to that address.

  8. ISR is executed. ISR pushes all the registers that it plans to use into stack to further save the context. Then it masks its IRQ in PIC.

  9. ISR knows the addresses of the device it serves. It reads the keypad’s data register with a LD instruction.

  10. As its data register is read, keypad makes its INT pin zero. Note that this may not result in the lowering of the PIC’s INT pin, as there may be other active I/O devices trying to interrupt CPU.

  11. ISR executes a STI instruction and makes IF=0, enabling interrupts again.

  12. ISR processes data. At this stage, it can receive other interrupts.

  13. ISR pops all regs, unmasks the IRQ in PIC, and executes a RTI. RTI pops the PC and flags registers, and restores the CPU to its state just before interrupt.

Note that here, for all intents and purposes, we are executing a multitasking program, as many interrups can execute on top of each other. Interrupt flag of the CPU and the mask register of PIC acts as mutexes. The rules are

  1. No two interrupts of the same kind (ie, with the same IRQ) can execute concurrently.
  2. Different interrupts can interrupt each other and can execute on top of each other.

Categories:CSE417