Introduction to Interrupts
Interrupts are an alternative to polling.
Why do we require interrupts?
Basic setup of interrupts
Basic steps of Interrupt processing
The following itemized list shows how an interrupt proceeds step by step. Things that happen in the I/O device is shown in red, if it happened in PIC it is blue, if happened in CPU hardware it is dark green, if happened in sortware it is black. We will take the keypad as an example device.
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If an I/O device requires service, it raises its INT pin.
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INT pins of all I/O devices are connected to IRQ pins of the PIC. If one or more of the PIC’s unmasked IRQ pins are raised, INT pin of the PIC is raised, which is connected to the INT pin of CPU. Hence the interrupt signal reaches the CPU.
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IRQ pins of the PIC are numbered from 0 to 7, and this number becomes the “interrupt vector” of the I/O device which is connected to that pin. For example, if the printer is connected to the 5th IRQ pin of PIC, the interrupt vector of the printer becomes 5. PIC also outputs this vector together with the INT signal.
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After receiving the INT signal from the PIC, if its interrupt flag is set, CPU will wait till an instruction boundary, and then, rather than starting a new instruction, it starts interrupt processing.
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CPU raises its INTACK pin to signal. This signals that CPU is ready to read the interrupt vector through its datain bus.
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The interrupt vector is read through CPU’s datain bus. At the same time, CPU disables all interrupts by making IF=0.
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Now CPU has the vector, and hence it identified which device interrupted. It pushes PC and FLAGS registers to stack. Then it goes to IDT and retrieves the address of the ISR of the interrupting device, and jumps to that address.
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ISR is executed. ISR pushes all the registers that it plans to use. Then it masks its IRQ in PIC.
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ISR knows the addresses of the device it serves. It reads the keypad’s data register with a LD instruction.
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As its data register is read, keypad makes its INT pin zero. Note that this may not result in the lowering of the PIC’s INT pin, as there may be other active I/O devices trying to interrupt CPU.
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ISR executes a STI instruction and makes IF=0, enabling interrupts again.
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ISR processes data. At this stage, it can receive other interrupts.
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ISR pops all regs, unmasks the IRQ in PIC, and executes a RTI. RTI pops the PC and flags fegisters, and restores the COU to its state just before interrupt.
Note that here, for all intents and purposes, we are executing a multitasking program. Interrupt flag of the CPU and the mask register of PIC acts as mutexes. The rules are
- No two interrupts of the same kind (ie, with the same IRQ) can execute concurrently.
- Different interrupts can interrupt each other and can execute on top of each other.