5. VERILOG TUTORIAL 2 : CIRCUIT SIMULATION WITH VERILOG
In the previous chapter, we have said that “…Verilog programs are not “run” after being compiled. Instead, the .blif file they generate is used to build a circuit….”. Well, this is only partially true.
Note that verilog programs (like the real circuits they simulate) have a concept of time..
There is an exception to what we have said above, ie, when the line ordering in the code becomes important and program 1 generates different results from program 2. This is the simulation mode. Unsurprisingly, in the simulation mode we make the Verilog program work like a C program. We will discuss the simulation mode and testbenches later..