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Interfacing Reptile to Memory

Our processor has an 12-bit address bus, hence can potentially address any memory location in the 000-FFF range. Let us indicate this by the following figure:

We have drawn that ghostly dashed figure, because in order to read or write a memory location it is necessary but insufficient that our processor is capable to address it. In addition, there must be a memory chip “occupying” that memory location.  Up till now, we have assumed that we have a single 4K memory chip occupying all the address space. To indicate it in figure

But memory chips cost money. It is quite possible that the designer does not need to use full 4K memory space. He may need only 1K of memory for the task at hand, or even less. Or he may need the full 4K, but he may have 4x1K chips rather than a single 4K chip. In all such situations, we must be able to design the correct interface between the memory chips and the the CPU. Below, we will examine a variety of scenarios, going from the simplest to the more complex.

A single 4K memory chip.

A single 1K memory chip.

Two 1K memory chips.